Transition Fault Test Generation for Non- Scan Sequential Circuits at Functional Level

The paper presents two functional fault models that are devoted for functional delay test generation for non-scan synchronous sequential circuits. The sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The value k defines the length of clock sequence. The method that allows determining the length of clock sequence is presented. The experimental results demonstrate the superiority of the delay test patterns generated at the functional level using the introduced functional fault models against the transition test patterns obtained at the gate level by deterministic test pattern generator. Especially, the functional delay test generation method is valuable for the circuits, when the long test sequences are needed in order to detect transition faults.